1. Field of the Invention
The present invention relates to a test circuit and a redundancy circuit for a storing circuit section of a semiconductor integrated circuit device.
2. Description of the Background Art
For example, Japanese Patent Application Laid-Open No. 8-94718 (1996) (U.S. Pat. No. 5,815,512) has disclosed a conventional test circuit and redundancy circuit for a storing circuit section of a semiconductor integrated circuit device.
FIGS. 71 to 74 are diagrams showing a conventional semiconductor integrated circuit constituted by an RAM comprising a test circuit and a redundancy circuit. FIG. 71 is a diagram showing a positional relationship between FIGS. 72 and 73, and FIGS. 72 and 73 are circuit diagrams showing a circuit structure of a conventional RAM. FIG. 74 is a circuit diagram showing an internal structure of each of scan flip-flops SFFC  less than i greater than  to SFFC  less than i+4 greater than  having comparing circuits illustrated in FIGS. 72 and 73.
As shown in FIG. 74, a comparator 201 is constituted by an EX-OR gate 202 and an NAND gate 203. The EX-OR gate 202 receives input data D and expectation data EXP at one of inputs and the other input respectively, and the NAND gate 203 has one of inputs connected to an output of the EX-OR gate 202 and receives a comparison control signal CMP at the other input. An output of the NAND gate 203 is sent as an output of the comparator 201.
An AND gate 204 has one of inputs connected to the output of the comparator 201, and a selector 205 has a xe2x80x9c0xe2x80x9d input for receiving a serial input (data) SI, a xe2x80x9c1xe2x80x9d input connected to an output of the AND gate 204 and a control input for receiving a test mode signal TM. Then, the selector 205 outputs, from an output section Y, a signal obtained from the xe2x80x9c1xe2x80x9d input/xe2x80x9c0xe2x80x9d input based on xe2x80x9c1xe2x80x9d/xe2x80x9c0xe2x80x9d of the test mode signal TM.
A selector 206 has a xe2x80x9c0xe2x80x9d input for receiving the input data D, a xe2x80x9c1xe2x80x9d input connected to the output section Y of the selector 205 and a control input for receiving a shift mode signal SM. Then, the selector 206 outputs, from the output section Y, a signal obtained from the xe2x80x9c1xe2x80x9d input/xe2x80x9c0xe2x80x9d input based on xe2x80x9c1xe2x80x9d/xe2x80x9c0xe2x80x9d of the shift mode signal SM. A signal obtained from the output section Y of the selector 206 is sent as output data P.
A D-FF (D flip-flop) 207 has a D input to which the output section Y of the selector 206 is connected, and receives a timing signal (clock signal) T at a toggle input T. A signal obtained from a Q output section is output as a data output Q and a serial output (data) SO to the outside and is fed back to the other input of the AND gate 204.
As shown in FIGS. 72 and 73, five scan flip-flops SFFC  less than i greater than  to SFFC  less than i+4 greater than  having a circuit structure shown in FIG. 74 are connected in series to have a scan path for an RAM test. In some cases, the scan flip-flop SFFC  less than   greater than  will be hereinafter referred to as an SFFC  less than   greater than .
More specifically, the SFFC  less than i+4 greater than  receives serial input data SIDO  less than i+4 greater than  as a serial input SI and has a serial output SO connected to a serial input SI of the SFFC  less than i+2 greater than . Similarly, the SFFC  less than i+2 greater than , the SFFC  less than i+1 greater than  and the SFFC  less than i greater than  are connected in series, and the serial output SO of the SFFC  less than i greater than  in a last stage is output as serial output data SODO  less than i greater than .
The SFFC  less than i greater than  to the SFFC  less than i+4 greater than  receive a shift mode signal SM, a test mode signal TM, a comparison control signal CMP and a timing control signal CKDO in common (the timing control signal CKDO is input as the timing signal T), and receive data outputs DO  less than i greater than  to DO  less than i+4 greater than  of an RAM 211 as respective input data D of the SFFC  less than i greater than  to SFFC  less than i+4 greater than . Respective data outputs P of the SFFC  less than i greater than  to the SFFC  less than i+3 greater than  are sent as data outputs P  less than i greater than  to P  less than i+3 greater than .
Moreover, the SFFCs  less than i greater than ,  less than i+2 greater than  and  less than i+4 greater than  receive expectation data EXPA as the expectation data EXP, and the SFFCs  less than i+1 greater than  and  less than i+3 greater than  receive expectation data EXPB as the expectation data EXP. In other words, an expectation of a comparing operation can be set to include even and odd bits having different values.
Selectors 230 to 233 constituting a redundancy-relieved output selecting circuit receive the data outputs DO  less than i greater than  to DO  less than i+3 greater than  at respective xe2x80x9c0xe2x80x9d inputs, receive data outputs DO  less than i+1 greater than  to DO  less than i+4 greater than  at respective xe2x80x9c1xe2x80x9d inputs, and receive output data F  less than i+1 greater than  to F  less than i+4 greater than  at respective control inputs. Then, outputs of the selectors 230 to 233 constituting a redundancy-relieved input selecting circuit are sent as redundancy-relieved data outputs XDO  less than i greater than  to XDO  less than i+3 greater than .
Each of AND gates 221 to 223 receives each of serial outputs SO  less than i+1 greater than  to SO  less than i+3 greater than  at one of inputs. The AND gate 221 receives an output of the AND gate 222 at the other input, the AND gate 222 receives an output of the AND gate 223 at the other input, and the AND gate 223 receives a serial output SO  less than i+4 greater than  at the other input. Then, the outputs of the AND gates 221 to 223 are sent as the output data F  less than i+1 greater than  to F  less than i+2 greater than  and the serial output SO  less than i+4 greater than  is sent as the output data F  less than i+4 greater than .
On the other hand, an OR gate 215 receives a redundancy-relieved data input XDI  less than i greater than  at one of inputs, and receives the output data F  less than i+1 greater than  at the other input. Selectors 234 to 236 receive redundancy-relieved data inputs XDI  less than i+1 greater than  to XDI  less than i+3 greater than  at respective xe2x80x9c0xe2x80x9d inputs, receive the redundancy-relieved data inputs XDI  less than i greater than  to XDI  less than i+2 greater than  at respective xe2x80x9c1xe2x80x9d inputs, and receive the output data F  less than i+2 greater than  to F  less than i+4 greater than  at respective control inputs. The selectors 230 to 236 output the signals to be received at the xe2x80x9c0xe2x80x9d/xe2x80x9c1xe2x80x9d inputs based on xe2x80x9c0xe2x80x9d/xe2x80x9c1xe2x80x9d of the signal received at the control inputs. Moreover, the OR gate 215 does not need to be essential.
Then, a scan path circuit DISCAN inputs an output of the OR gate 215 as input data XI  less than i greater than , the outputs of the selectors 234 to 236 as input data XI  less than i+1 greater than  to  less than i+3 greater than , and a redundancy-relieved data input XDI  less than i+4 greater than  as input data XI  less than i+4 greater than .
The scan path circuit DISCAN receives a control signal CTRL including serial input data SIDI  less than i+4 greater than  and outputs serial output data SIDO  less than i greater than , and outputs input data DI  less than i greater than  to DI  less than i+4 greater than  to a 5-bit input section for the input data DI  less than i greater than  to DI  less than i+4 greater than  of the RAM 211.
FIG. 75 is a circuit diagram showing an internal structure of the scan path circuit DISCAN. As shown in FIG. 75, scan flip-flops SFFDI  less than i greater than  to SFFDI  less than i+4 greater than  are connected in series. In some cases, the scan flip-flop SFFDI  less than   greater than  will be hereinafter referred to as an SFFDI  less than   greater than .
FIG. 76 is a circuit diagram showing an internal structure of the scan flip-flop SFFDI  less than   greater than  illustrated in FIG. 75. As shown in FIG. 76, the SFFDI  less than   greater than  is constituted by a selector 241 and a D-FF 242, and the selector 241 receives input data D at a xe2x80x9c0xe2x80x9d input, receives a serial input SI at a xe2x80x9c1xe2x80x9d input and receives a shift mode signal SM at a control input. A signal obtained from an output section Y of the selector 241 is given to a D input of the D-FF 242 and is output as a data output P. The D-FF 242 receives a timing signal T at a toggle input T and sends a data output Q and a serial output SO from a Q output.
Returning to FIG. 75, the SFFDI  less than   greater than  is sequentially connected in series in order of the SFFDI  less than i+4 greater than  to the SFFDI  less than i greater than , and the SFFDI  less than i+4 greater than  receives the serial input data SIDI  less than i+4 greater than  as a serial input SI and the SFFDI  less than i greater than  outputs serial output data SIDO  less than i greater than  as a serial output SO.
Shift mode input data SMDI are input as the shift mode signal SM of the SFFDI  less than i greater than  to the SFFDI  less than i+4 greater than  in common, and clock data CKDI are input as the timing signal T in common. The redundancy-relieved data inputs XI  less than i greater than  to XI  less than i+4 greater than  are sent as the input data D of the SFFDI  less than i greater than  to SFFDI  less than i+4 greater than . The serial input data SIDI  less than i+4 greater than , the shift mode input data SMDI and the clock data CKDI are equivalent to the control signal CTRL in FIG. 72.
When the RAM 211 is to be tested, write data are set by using the scan path circuit DISCAN. In the examples of FIGS. 72 and 73, the RAM 211 has address inputs A  less than 0 greater than  to  less than 3 greater than  for 4 bits, a write control signal WE for 1 bit, data output signals DO  less than i greater than  to DO  less than i+4 greater than  for 5 bits and data input signals DI  less than i greater than  to DI  less than i+4 greater than .
Next, an RAM test operation using the above-mentioned structure will be described.
(1) Before the RAM test is carried out, xe2x80x9c1xe2x80x9d is shifted in from an SIDO terminal (SIDO  less than i+4 greater than ) in a state of xe2x80x9cTM1=0, SM=1xe2x80x9d (5 clocks are required for a 5-bit scan path as in this example).
As a result, respective serial outputs SO are set to be xe2x80x9cSO  less than i greater than =1, SO  less than i+1 greater than =1, SO  less than i+2 greater than =1, SO  less than i+3 greater than =1, SO  less than i+4 greater than =1xe2x80x9d at the SFFC  less than i greater than  to the SFFC  less than i+4 greater than .
(2) In a state of xe2x80x9cTM1=1, SM=1xe2x80x9d, the RAM test is carried out for all addresses. While data for the test are written or read, an expectation EXP (EXPA, EXPB) and a comparison control signal CMP (comparison with CMP=1) are controlled appropriately.
As a result, if there are failures (the expectations EXPA and EXPB are different from the data output DO  less than   greater than  of the RAM), an output of the comparator 201 of the SFFC  less than   greater than  is set to be xe2x80x9c0xe2x80x9d and the D-FF 207 is reset to be xe2x80x9c0xe2x80x9d synchronously with a clock signal T.
For example, in the case in which a failure is detected at the SFFC  less than i+2 greater than  corresponding to the data output DO  less than i+2 greater than  of the RAM 211, the serial output SO  less than i+2 greater than =xe2x80x9c0xe2x80x9d is obtained (SO  less than i greater than , SO  less than i+1 greater than , SO  less than i+2 greater than  and SO  less than i+4 greater than  are maintained to be xe2x80x9c1xe2x80x9d).
(3) In a state of xe2x80x9cTM1=0, SM=1xe2x80x9d, a test result is shifted out from an SODO terminal (SODO  less than i greater than ).
In the case in which an RAM redundancy relief operation is to be carried out, the RAM test operations (1) and (2) are executed and a control signal F  less than   greater than  of the selector is then kept.
For example, in the case in which a failure is detected at the SFFC  less than i+2 greater than  corresponding to the output data DO  less than i+2 greater than  of the RAM, the SO  less than i+2 greater than =xe2x80x9c0xe2x80x9d is obtained as described above (SO  less than i greater than , SO  less than i+1 greater than , SO  less than i+3 greater than  and SO  less than i+4 greater than  are maintained to be xe2x80x9c1xe2x80x9d).
Accordingly, the control signals of the selectors 230 to 233 are set to be xe2x80x9cF less than i+4 greater than =1, F  less than i+2 greater than =1, F  less than i+2 greater than =0, F  less than i+1 greater than =0xe2x80x9d. As a result, the selection control data of the selectors 230 to 233 are determined, and the output data DO  less than i+4 greater than , DO  less than i+3 greater than , DO  less than i+1 greater than  and DO  less than i greater than  are connected to redundancy-relieved data outputs XDO  less than i+3 greater than , XDO  less than i+2 greater than , XDO  less than i+1 greater than  and XDO  less than i greater than  respectively, and the output data DO  less than i+2 greater than  having a failure are not used. Similarly, the selection control data of the selectors 234 to 236 are determined, and the redundancy-relieved data input XDI  less than i+3 greater than , XDI  less than i+2 greater than , XDI  less than i+1 greater than  and XDI  less than i greater than  are connected to the data inputs DI  less than i+4 greater than , DI  less than i+3 greater than  and DI  less than i+2 greater than , DI  less than i+1 greater than , and DI  less than i greater than  respectively.
By the above-mentioned connection switching, even if a memory circuit corresponding to the output data DO  less than i+2 greater than  has a failure in the RAM 211, it normally operates as an RAM having a 4-bit input and output.
Referring to the data input and output, if the same circuit is provided for two systems (in the above-mentioned example, i=0 (data outputs DO  less than 0 greater than  to DO  less than 4 greater than ), i=5 (data outputs DO  less than 5 greater than  to DO  less than 9 greater than ), it is also possible to constitute the RAM 211 capable of relieving 1 bit for i=0 and 1 bit for i=5, that is, 2 bits in total. In this case, a 10-bit RAM is used for an 8-bit input and output in a normal operation.
The RAM comprising the conventional test circuit has the following problems (1) to (3).
(1) The normal and abnormal operations of the selectors 230 to 233 for the redundancy-relieved data output XDO  less than   greater than  cannot be tested.
(2) When the test results are shifted out from the SFFC  less than i greater than  to SFFC  less than i+4 greater than  in order to judge pass/fail of redundancy relief, the contents of the redundancy control data F  less than i greater than  to F  less than i+4 greater than  to be the test results are eliminated.
(3) Since the test result compressed as a serial output SO is shifted out, it is hard to carry out failure analysis using a memory test device.
A first aspect of the present invention is directed to a semiconductor integrated circuit comprising a storing circuit for outputting output data having a first number of bits, a redundancy-relieved output selecting circuit for selecting output data having a second number of bits which are smaller than the first number of bits from the output data having the first number of bits in accordance with selection control data and for outputting redundancy-relieved output data having the second number of bits, the selection control data are switched based on a redundancy control signal during a redundancy relief operation, and a flip-flop group for inputting the redundancy-relieved output data having the second number of bits, the redundancy control signal being determined based on keeping data in the flip-flop group.
A second aspect of the present invention is directed to the semiconductor integrated circuit according to the first aspect of the present invention, further comprising a selection content setting device for forcibly setting the selection control data of the redundancy-relieved output selecting circuit during a redundancy-relieved output selecting circuit test.
A third aspect of the present invention is directed to the semiconductor integrated circuit according to the second aspect of the present invention, wherein the flip-flop group includes the first number of flip-flops capable of executing a comparing operation for obtaining a result of comparison by comparing one of the redundancy-relieved output data and the output data with expectation data, the first number of flip-flops includes the second number of flip-flops setting redundancy-relieved output data having the second number of bits to be the keeping data respectively and a third number of flip-flops setting the output data having a third number of bits out of the output data having the first number of bits to be the keeping data respectively, and the third number has a number obtained by subtracting the second number from the first number.
A fourth aspect of the present invention is directed to the semiconductor integrated circuit according to the third aspect of the present invention, wherein the comparing operation is revoked during the redundancy-relieved output selecting circuit test in the third number of flip-flops.
A fifth aspect of the present invention is directed to the semiconductor integrated circuit according to any of the first to fourth aspects of the present invention, further comprising a switching information storing device provided between the flip-flop group and the redundancy-relieved output selecting circuit for storing a switching information.
A sixth aspect of the present invention is directed to the semiconductor integrated circuit according to the first aspect of the present invention, wherein the storing circuit has the first number of data input sections for fetching input data having the first number of bits, the semiconductor integrated circuit further comprising a redundancy-relieved input selecting circuit for receiving a redundancy-relieved input data having the second number of bits and for giving the redundancy-relieved input data having the second number of bits to the second number of data input sections out of the first number of data input sections based on the redundancy control signal during the redundancy relief operation.
A seventh aspect of the present invention is directed to the semiconductor integrated circuit according to the sixth aspect of the present invention, further comprising a selection content setting device for forcibly setting the selection control data of the redundancy-relieved input selecting circuit during a redundancy-relieved input selecting circuit test.
An eighth aspect of the present invention is directed to the semiconductor integrated circuit according to the sixth or seventh aspect of the present invention, further comprising the first number of data holding sections provided between the storing circuit and the redundancy-relieved input selecting circuit corresponding to the first number of data input sections, the first number of data holding sections being brought into a hold state in which the redundancy-relieved input selecting circuit holds its own keeping data when the selection control data of the redundancy-relieved input selecting circuit is a predetermined selection control data.
A ninth aspect of the present invention is directed to the semiconductor integrated circuit according to the sixth or seventh aspect of the present invention, wherein the flip-flop group includes the first number of scan flip-flops provided corresponding to the output data having the first number of bits, the first number of scan flip-flops are connected in series from a first stage to a last stage so that a shift operation of serial data can be carried out, the semiconductor integrated circuit further comprising the first number of data holding sections provided corresponding to the first number of data input sections and having a count function for counting the first number by a serial operation; and a control device for a storing circuit test for carrying out a 1-bit loop processing the first number of times in accordance with a count result obtained by the count function of the first number of data holding sections, in which test results of the output data having the first number of bits are held as keeping data of the first number of scan flip-flops respectively and the first number of scan flip-flops are then caused to carry out a shift operation for 1 bit, thereby outputting serial output data of the scan flip-flop in the last stage to an outside and feeding back the serial output data as a serial data input of the scan flip-flop in the first stage during a storing circuit test.
A tenth aspect of the present invention is directed to the semiconductor integrated circuit according to the ninth aspect of the present invention, wherein the first number of data holding sections are brought into a hold state in which the redundancy-relieved input selecting circuit holds its own keeping data, when the selection control data of the redundancy-relieved input selecting circuit is a predetermined selection control data.
An eleventh aspect of the present invention is directed to the semiconductor integrated circuit according to the third aspect of the present invention, further comprising a first multiplexer section for classifying two or more output data having a first bit number sent from the first number of flip-flops into a fourth number of first groups which is smaller than the first number and for outputting one of the output data of the flip-flops in the first group as first selection output data based on a first selection signal obtained from an outside in the fourth number of first groups respectively, thereby outputting the first selection output data having the fourth number of bits.
A twelfth aspect of the present invention is directed to the semiconductor integrated circuit according to the eleventh aspect of the present invention, further comprising a selection content setting device for forcibly setting the selection control data of the redundancy-relieved output selecting circuit during a redundancy-relieved output selecting circuit test, wherein the selection content setting device and the first multiplexer section partially sharing a component.
A thirteenth aspect of the present invention is directed to the semiconductor integrated circuit according to the eleventh or twelfth aspect of the present invention, further comprising a second multiplexer section for classifying two or more first selection output data having the fourth number of bits into a fifth number of second groups which is smaller than the fourth number and for outputting one of the first selection output data in the second group as second selection output data based on a second selection signal obtained from an outside in the fifth number of second groups respectively, thereby outputting the second selection output data having the fifth number of bits.
According to the first aspect of the present invention, the flip-flop group for inputting the redundancy-relieved output data having the second number of bits is provided. Therefore, the selection control data of the redundancy-relieved output selecting circuit are properly switched in response to the redundancy control signal determined based on the keeping data of the flip-flop group, thereby causing the flip-flop group to newly keep the second number of redundancy-relieved output data. Consequently, it is possible to carry out a pass/fail judgement of the selecting operation of the redundancy-relieved output selecting circuit comparatively easily.
According to the second aspect of the present invention, the selection control data of the redundancy-relieved output selecting circuit can be set forcibly during the redundancy-relieved output selecting circuit test through the selection content setting device. Consequently, the selection control data can easily be set without using the redundancy control signal.
According to the third aspect of the present invention, the selection control data of the redundancy-relieved output selecting circuit are properly switched so that the result of the comparison of the redundancy-relieved output data with the expectation data is obtained by the second number of flip-flops. Consequently, it is possible to carry out a pass/fail judgement of the selecting operation of the redundancy-relieved output selecting circuit comparatively easily.
According to the fourth aspect of the present invention, the comparing function of the third number of flip-flops is revoked during the redundancy-relieved output selecting circuit test. Consequently, it is possible to avoid a drawback caused by the execution of the comparing operation through the third number of flip-flops which do not contribute to the redundancy-relieved output selecting circuit test.
According to the fifth aspect of the present invention, the switching information storing device is further provided. Consequently, the flip-flop group can be used as a temporary storing section for the redundancy-relieved output data of the storing circuit.
According to the sixth aspect of the present invention, the selection control data of the redundancy-relieved input selecting circuit are properly switched in response to the redundancy control signal determined based on the keeping data of the flip-flop group and the redundancy-relieved input data having the second number of bits are input to the storing circuit and are then output as the redundancy-relieved output data having the second number of bits from the storing circuit and the flip-flop group is caused to newly hold them. Consequently, it is possible to carry out a pass/fail judgement of the selecting operation of the redundancy-relieved input selecting circuit comparatively easily.
According to the seventh aspect of the present invention, the selection control data of the redundancy-relieved input selecting circuit can be set forcibly during the redundancy-relieved input selecting circuit test through the selection content setting device. Consequently, the selection control data can easily be set without using the redundancy control signal.
According to the eighth aspect of the present invention, the first number of data holding sections can be utilized as temporary storing sections for the redundancy-relieved input data.
According to the ninth aspect of the present invention, the control device for a storing circuit test carries out a 1-bit loop processing the first number of times in which the serial output data of the scan flip-flop in the last stage are output to the outside and are fed back as the serial data input of the scan flip-flip in the first stage. Consequently, after the test results are output as the serial output data, the keeping data of the first number of scan flip-flops can be returned to the original test result hold state.
According to the tenth aspect of the present invention, the first number of data holding sections can be utilized as temporary storing sections for the redundancy-relieved input data.
According to the eleventh aspect of the present invention, the output data having the first number of bits are multiplex output as the first selection output data having the fourth number of bits which are smaller through the first multiplexer section. Consequently, the output data having the first number of bits can be sent as the first selection output data without compressing the data contents.
According to the twelfth aspect of the present invention, the selection content setting device and the first multiplexer section partially share the component. Consequently, the structure of the device can be simplified.
According to the thirteenth aspect of the present invention, the first selection output data having the fourth number of bits are multiplex output as the second selection output data having the fifth number of bits which are smaller through the second multiplexer section. Consequently, the first selection output data having the fourth number of bits can be sent as the second selection output data without compressing the data contents.
An object of the present invention is to provide a semiconductor integrated circuit having a test circuit and a redundancy circuit which can execute a pass/fail test for a selecting operation of a redundancy-relieved output selecting circuit for selecting redundancy-relieved output data. These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.